simulate_verilog
Simulate Verilog designs and testbenches using Icarus Verilog to validate functionality, analyze outputs, and debug hardware behavior. Integrates with EDA Tools MCP Server for comprehensive electronic design automation workflows.
Instructions
Simulate Verilog code using Icarus Verilog
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| testbench_code | Yes | The testbench code | |
| verilog_code | Yes | The Verilog design code |